Because of the invention of integrated circuits, the semiconductor industry has experienced continuous rapid growth due to constant improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.) and semiconductor packages. For the most part, these improvements in integration density have come from repeated reductions in minimum feature size, allowing more components to be integrated into a semiconductor chip or package.
One approach for allowing more components to be integrated into a semiconductor package is the adoption of Bump-on-Trace (BOT) structures. BOT structures are used in flip chip packages, wherein metal bumps (for supporting device dies) directly land on metal traces of package substrates instead of being disposed on metal pads that have greater widths than the metal traces. The advantages of BOT structures include a smaller chip area requirement and low manufacturing cost.
For BOT structures, the mismatch between the coefficient of thermal expansions (CTE) of the semiconductor chip and the package substrate may result in stress on the metal traces, causing the metal traces to peel off from the package substrate. In addition, for BOT structures with finer bump pitches (the distance between adjacent bonding bumps), since the width of the conductive traces decreases, the bonding force between conductive traces and the package substrate is smaller, which also causes the peeling off of the metal traces. In view of the above, there is a need to solve the aforementioned problems, as well as other deficiencies in conventional BOT structures.